1. Field of the Invention
The invention relates to an embedded memory device, and more particularly to a gate process and a gate structure of an embedded memory device in order to prevent damage to a tunnel oxide and a dielectric structure in a memory array area in a subsequent cleaning process for removing a native oxide layer.
2. Description of the Related Art
An embedded memory device, called a SOC (system on a chip) device, integrates memory cells and logic circuits on the same substrate, in which the memory data stored in the memory area is operated by logic circuits. Currently in the semiconductor industry, a DRAM (dynamic random access memory) cell, an SRAM (static random access memory) cell, and a flash memory cell are extensively used in embedded memory devices.
The flash memory cell comprises a floating gate for storing charge and a control gate for controlling the voltage of a world line, in which the voltages of the word line and source/drain electrodes are coordinated to control the charge-stored capacity of the floating gate and determine the on/off state of a transistor. Thus, the flash memory is also called an erasable programmable read only memory (EPROM). In a conventional gate process for the flash memory device, a tunnel oxide film is formed between a silicon substrate and a floating gate, and then an ONO dielectric structure and a control gate are successively formed on the floating gate. The quality control of the tunnel oxide film is one important factor in the operating speed of the flash memory. In many approaches for combining the memory process and the standard logic process, however, the formation of a gate oxide in the peripheral logic area causes damage to the tunnel oxide in the memory area, thus deteriorating the electrical performance of the flash memory.
FIGS. 1A to 1D are cross-sections illustrating a conventional gate process for an embedded memory device. In FIG. 1A, a semiconductor silicon substrate 10 is provided with a memory cell area I and a logic circuit area II. First, a first silicon oxide layer 12 is grown on the semiconductor silicon substrate 10, and then a gate structure 20 used for a flash memory device is formed on the memory cell area I. The gate structure 20 comprises a floating gate layer 14, an ONO dielectric layer 16 and a control gate layer 18. Thus, the first silicon oxide layer 12 sandwiched between the gate structure 20 and the semiconductor silicon substrate 10 serves as a tunnel oxide layer 12a. Next, in FIG. 1B, using deposition and dry etching, a silicon oxide spacer 22 is formed on the sidewall of the gate structure 20.
Next, in FIG. 1C, a pre-cleaning process is performed on the semiconductor silicon substrate 10 to remove the first silicon oxide layer 12 outside the gate structure 20. Next, in FIG. 1D, a thermal oxidation process is employed to grow a second silicon oxide layer 24 on the entire surface of the substrate 10. Finally, using deposition, photolithography and etching, a gate layer 26 is formed on the second silicon oxide layer 24 within the logic circuit area II, in which the second silicon oxide layer 24 sandwiched between the gate layer 26 and the substrate 10 serves as a gate oxide layer 24a. 
The pre-cleaning process is used to remove a native oxide layer from the logic circuit area II, which is beneficial for the subsequent gate oxide process. In dipping the substrate 10 into an etching solution used in the pre-cleaning process, however, the etching solution damage the silicon oxide spacer 22, even the tunnel oxide layer 12a and the ONO dielectric layer 16, thus losing control of the thickness and film quality of the tunnel oxide layer 12a. Accordingly, a novel gate process for preventing damage to the tunnel oxide layer 12a and the ONO dielectric layer 16 in the subsequent cleaning process is called for.